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rev.3.00, oct.09. 2003, page 1 of 12 HD74CDCV857A 2.5-v phase-lock loop clock driver rej03d0136?0300z (previous ade-205-693b (z)) rev.3.00 oct.09.2003 description the HD74CDCV857A is a high-performance, low-skew, lo w-jitter, phase locked loop clock driver. it is specifically designed for use with ddr (double data rate) synchronous drams. features ? ddr333 / pc2700-compliant, also meets ddr266 / pc2100 requirement. ? supports 60 mhz to 170 mhz operation range ? distributes one differential clock input pair to ten differential clock outputs pairs ? supports spread spectrum clock requirements meeting the pc100 sdram registered dimm specification ? external feedback pins (fbin, fbin ) are used to synchronize the outputs to the clock input ? supports 2.5v analog supply voltage (av cc ), and 2.5 v v ddq ? no external rc network required ? sleep mode detection ? 48pin tssop (thin shrink small outline package) function table inputs : outputs avcc pwrdwn clk clk :y y fbout fbout :pll gnd h l h : lhlh : bypassed / off *1 gnd h h l : hl hl : bypassed / off *1 xl l h : zzzz : off xl h l : zzzz : off 2.5 v h l h : lhlh : on 2.5 v h h l : hl hl : on 2.5 v x input clock frequency 60 to 170 mhz 0 mhz : zzzz : off h : high level l : low level x : don?t care z : high impedance notes: 1. bypassed mode is used for renesas test mode.
HD74CDCV857A rev.3.00, oct.09. 2003, page 2 of 12 pin arrangement (top view) 1 2 3 4 5 6 7 8 9 10 gnd gnd clk clk gnd gnd gnd y0 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 y0 y1 y1 y2 y2 y3 y3 y4 y4 gnd y9 y9 y8 y8 fbin fbin fbout fbout pwrdw n y7 y7 gnd gnd gnd y6 y6 y5 gnd y5 v ddq v ddq v ddq v ddq v ddq v ddq v ddq v ddq v ddq av agnd cc
HD74CDCV857A rev.3.00, oct.09. 2003, page 3 of 12 pin function pin name no. type description agnd 17 ground analog ground. agnd provid es the ground reference for the analog circuitry. av cc 16 power analog power supply. av cc provides the power reference for the analog circuitry. in addition, av cc can be used to bypass the pll for test purposes. when av cc is strapped to ground, pll is bypassed and clk is buffered directly to the device outputs. this bypass mode is used for renesas test. clk, clk 13, 14 i differential input clock input. clk provides the clock signal to be distributed by the HD74CDCV857A clock driver. clk is used to provide the reference signal to the integrated pll that generates the clock output signals. clk must have a fixed frequency and fixed phase for the pll to obtain phase lock. once the circuit is powered up and a valid clk signal is applied, a stabilization time is required for the pll to phase lock the feedback signal to its reference signal. fbin , fbin 35, 36 i differential input feedback input. fbin provides the feedback signal to the internal pll. fbin must be hard-wired to fbout to complete the pll. the integrated pll synchronizes clk and fbin so that there is nominally zero phase error between clk and fbin. fbout, fbout 32, 33 o differential output feedback output. fbout is dedicate d for external feedback. it switches at the same frequency as clk. when externally wired to fbin, fbout completes the feedback loop of the pll. pwrdwn 37 i output bank enable. pwrdwn is the output enable for all outputs. when pwrdwn is low, vco will stop and all outputs are disabled to a high impedance state. when pwrdwn will be returned high, pll will re-synchroniz to clk frequency and all outputs are enabled. gnd 1, 7, 8, 18, 24, 25, 31, 41, 42, 48 ground ground v ddq 4, 11, 12, 15, 21, 28, 34, 38, 45 power power supply y 3, 5, 10, 20, 22, 27, 29, 39, 44, 46 o differential output clock outputs. these outputs pr ovide low-skew copies of clk. y 2, 6, 9, 19, 23, 26, 30, 40, 43, 47 o differential output clock outputs. these outputs provide low-skew copies of clk .
HD74CDCV857A rev.3.00, oct.09. 2003, page 4 of 12 logic diagram pll pow e r d ow n a n d t est lo g i c 37 c l k av cc c l k pwrdwn 1 6 1 3 14 36 35 fbin fbin y 0 y 0 3 2 5 6 1 0 9 2 0 1 9 22 2 3 4 6 47 44 4 3 3 9 40 2 9 30 27 2 6 32 33 y1 y1 y2 y2 y 3 y 3 y4 y4 y 5 y 5 y 6 y 6 y7 y 7 y 8 y 8 y9 y 9 fb out fb out ddq note: all inputs and outputs are associated with v = 2.5 v.
HD74CDCV857A rev.3.00, oct.09. 2003, page 5 of 12 absolute maximum ratings item symbol ratings unit conditions supply voltage v ddq ?0.5 to 3.6 v input voltage v i ?0.5 to v ddq +0.5 v output voltage *1 v o ?0.5 to v ddq +0.5 v input clamp current i ik ?50 ma v i < 0 output clamp current i ok ?50 ma v o < 0 continuous output current i o 50 ma v o = 0 to v ddq supply current through each v ddq or gnd i vddq or i gnd 100 ma maximum power dissipation at ta = 55c (in still air) 0.7 w storage temperature t stg ?65 to +150 c notes: stresses beyond those listed under ?absol ute maximum ratings? may cause permanent damage to the device. these are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated un der ?recommended operating conditions? is not implied. exposure to absolute maximum rated c onditions for extended periods may affect device reliability. 1. the input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed.
HD74CDCV857A rev.3.00, oct.09. 2003, page 6 of 12 recommended operating conditions item symbol min typ max unit conditions notes output supply voltage v ddq 2.3 2.5 2.7 v supply voltage av cc v ddq ?0.12 v ddq 2.7 v dc input signal voltage v in ?0.3 ? v ddq +0.3 v all pins 1 high level input voltage v ihg 1.7 ? v ddq +0.3 v pwrdwn input pin low level input voltage v ilg ?0.3 ? 0.7 v pwrdwn input pin input differential voltage v id 0.36 ? v ddq +0.6 v 3 output differential voltage v o d 0.70 ? v ddq +0.6 v input differential-pair cross voltage v ix v ddq /2 ?0.2 ? v ddq /2 +0.2 v 2, 3 output differential-pair cross voltage v ox v ddq /2 ?0.15 ? v ddq /2 +0.15 v 2, 3 i oh ? ? ?12 ma output current i ol ??12ma input clock slew rate t sl(i) 1 ? 4 v/ns 20% ? 80% 3 operating temperature t a 0?70c 3 notes: inputs pins must be prevent from floating. feedback inputs (fbin, fbin ) may float when the device is in low power mode. 1. dc input signal voltage specifies the allo wable dc execution of differential input. 2. differential cross point voltage is expected to track variations of v ddq and is the voltage at which the differential signals must be crossing. (see figure1) 3. guaranteed by design, not 100% tested in production. crossing point clk clk id v figure 1 differential input levels
HD74CDCV857A rev.3.00, oct.09. 2003, page 7 of 12 electrical characteristics item symbol min typ *1 max unit test conditions notes input clamp voltage clk, clk fbin, fbin , g v ik ? ? ?1.2 v i i = ?18 ma, v ddq = 2.3 v v ddq ?0.1 ? ? i oh = ?100 a, v ddq = 2.3 to 2.7 v v oh 1.7 ? ? i oh = ?12 ma, v ddq = 2.3 v ??0.1 i ol = 100 a, v ddq = 2.3 to 2.7 v output voltage v ol ??0.6 v i ol = 12 ma, v ddq = 2.3 v input current i i ?10 ? 10 a v i = 0 v to 2.7 v, v ddq = 2.7 v input capacitance c i ? 2.5 ? pf clk and clk , fbin and fbin 2 di cc ? 200 350 supply current ai cc ?912 ma f = 170 mhz, v ddq = av cc = 2.7 v 3 supply current in power down mode i ccpd ? 100 200 a note: 1. for conditions shown as min or max, us e the appropriate value specified under recommended operating conditions. 2. guaranteed by design, not 100% tested in production. 3. all outputs are loaded as shown in figure2.
HD74CDCV857A rev.3.00, oct.09. 2003, page 8 of 12 switching characteristics item symbol min typ max unit test conditions notes period jitter t per ?75 ? 75 ps see figure 6, 9 7, 8 half period jitter t hper ?100 ? 100 ps see figure 7, 9 8, 10 cycle to cycle jitter t cc ?75 ? 75 ps see figure 5, 9 10 static phase offset t spe ?50 ? 50 ps see figure 3, 9 4, 5, 9, 10 output clock skew t sk ? ? 100 ps see figure 4, 9 operating clock frequency f clk(o) 60 ? 200 mhz see figure 9 1, 2 application clock frequency f clk(a) 80 167 170 mhz see figure 9 1, 3 input clock duty cycle t dc 40 ? 60 % 10 output clock slew rate t sl(o) 1.0 ? 2.0 v/ns see figure 9 20% ? 80% pll stabilization time t stab ? ? 0.1 ms see figure 9 6, 10 ssc modulation frequency 30 ? 50 khz 10 ssc clock input frequency deviation 0.00 ? ?0.50 % 10 pll loop bandwidth ? 3 ? mhz 10 notes: 1. the pll must be able to handle spread spectrum induced skew (the specification for this frequency modulation can be found in the latest intel pc100 registered dimm specification) 2. operating clock frequency indicates a range ov er which the pll must be able to lock, but in which it is not required to me et the other timing parameters. 3. application clock frequency indicates a rang e over which the pll must meet all timing parameters. 4 assumes equal wire length and loading on the clock output and feedback path. 5. static phase offset does not include jitter. 6. stabilization time is the time required for the integrated pll circuit to obtain phase lock of its feedback signal to its reference signal after power up. 7. period jitter defines the largest variation in clock period, around a nominal clock period. 8. period jitter and half?period jitter are independent from each other. 9. conditions at v ddq = 2.5 v, ta = 25c. 10. guaranteed by design, not 100% tested in production.
HD74CDCV857A rev.3.00, oct.09. 2003, page 9 of 12 differential clock outputs are directly terminated by a 120 ? resistor. figure 2 is typical usage conditions of outputs load. out out v device under test ddq v ddq r = 120 ? t c = 14 pf c = 14 pf figure 2 differential signal using direct termination resistor clkin fbin spe t c lkin fbin figure 3 static phase offset fbout yx sk t yx yx' sk t f bout yx yx yx ' figure 4 output skew
HD74CDCV857A rev.3.00, oct.09. 2003, page 10 of 12 yx, fbout yx , fbout cycle n t cc cycle n cycle n+1 t = t - t cycle n+1 t figure 5 cycle to cycle jitter yx, fbout yx , fbout cycle n t per cycle n t = t - yx, fbout yx , fbout o f 1 o f 1 figure 6 period jitter yx, fbout yx , fbout half period n t half period n+1 t half period n hper t = t - yx, fbout yx , fbout o f 1 o 2*f 1 figure 7 half period jitter
HD74CDCV857A rev.3.00, oct.09. 2003, page 11 of 12 yx , fbout yx, fbout t = t - t hcc t half cycle n t half cycle n+1 half cycle n half cycle n+1 figure 8 half cycle to cycle jitter out out v device under test ddq v /2 ddq -v /2 ddq r = 10 ? t r = 50 ? t r = 50 ? t r = 10 ? t r = 120 t z = 60 ? z = 60 ? c = 14 pf -v /2 ddq -v /2 ddq c = 14 pf oscillo scope av cc av /2 cc agnd gnd z = 50 ? z = 50 ? out out v device under test ddq v ddq z = 60 ? z = 60 ? c = 14 pf c = 14 pf av cc av cc agnd gnd figure 9 output load test circuit
HD74CDCV857A rev.3.00, oct.09. 2003, page 12 of 12 package dimensions package code jedec jeita mass (reference value) ttp?48dbv ? ? 0.20 g *pd plating 0.08 m 0.10 *0.15 0.05 8.10 0.20 0.50 0.1 0.65 max 124 25 48 12.5 6.10 0? ? 8? 0.50 1.20 max 0.10 0.05 12.7 max 1.0 *0.19 0.05 as of january, 2002 unit: mm
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